
// Library name: Project
// Cell name: NAND
// View name: schematic
subckt NAND AN AP BN BP HiOut LoOut VDD\+ VDD\- VSS\+ VSS\-
    M3 (net9 BN VSS\- VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M2 (LoOut AN net9 VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M1 (net17 BN VSS\+ VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M0 (HiOut AN net17 VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M7 (HiOut BP VDD\+ VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M6 (HiOut AP VDD\+ VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M5 (LoOut BP VDD\- VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M4 (LoOut AP VDD\- VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
ends NAND
// End of subcircuit definition.

// Library name: Project
// Cell name: DelVGate
// View name: schematic
subckt DelVGate HiOut LoOut NIN PIN VDD\+ VDD\- VSS\+ VSS\-
    M1 (LoOut PIN VDD\- VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M0 (HiOut PIN VDD\+ VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M3 (LoOut NIN VSS\- VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M2 (HiOut NIN VSS\+ VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends DelVGate
// End of subcircuit definition.

// Library name: Project
// Cell name: NOR
// View name: schematic
subckt NOR AN AP BN BP HiOut LoOut VDD\+ VDD\- VSS\+ VSS\-
    M8 (LoOut BN VSS\- VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M2 (LoOut AN VSS\- VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M1 (HiOut BN VSS\+ VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M0 (HiOut AN VSS\+ VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M7 (net32 AP VDD\- VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M6 (LoOut BP net32 VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M5 (HiOut BP net36 VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M4 (net36 AP VDD\+ VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
ends NOR
// End of subcircuit definition.

// Library name: Project
// Cell name: SupplyBiasXor
// View name: schematic
subckt SupplyBiasXor AH AL BH BL HiOut LoOut Vdd Vdd\- Vss Vss\+
    I0 (AH AL BH BL net13 net14 Vdd Vdd\- Vss\+ Vss) NAND
    I1 (net23 net24 net13 net14 Vdd Vdd\- Vss\+ Vss) DelVGate
    I3 (net41 net42 net23 net24 HiOut LoOut Vdd Vdd\- Vss\+ Vss) NOR
    I2 (AH AL BH BL net41 net42 Vdd Vdd\- Vss\+ Vss) NOR
ends SupplyBiasXor
// End of subcircuit definition.

// Library name: Project
// Cell name: SupplyBiasFullAdder
// View name: schematic
subckt SupplyBiasFullAdder Ah Al Bh Bl COutH COutL CinH CinL SumH SumL Vdd \
        Vdd\- Vss Vss\+
    I1 (net30 net31 CinH CinL SumH SumL Vdd Vdd\- Vss Vss\+) SupplyBiasXor
    I0 (Ah Al Bh Bl net30 net31 Vdd Vdd\- Vss Vss\+) SupplyBiasXor
    I4 (net46 net47 net56 net57 COutH COutL Vdd Vdd\- Vss\+ Vss) NAND
    I3 (CinH CinL net30 net31 net46 net47 Vdd Vdd\- Vss\+ Vss) NAND
    I2 (Ah Al Bh Bl net56 net57 Vdd Vdd\- Vss\+ Vss) NAND
ends SupplyBiasFullAdder
// End of subcircuit definition.

// Library name: Project
// Cell name: 8BitRippleCarryAdder
// View name: schematic
subckt Project_8BitRippleCarryAdder_schematic Ah0 Ah1 Ah2 Ah3 Ah4 Ah5 Ah6 \
        Ah7 Al0 Al1 Al2 Al3 Al4 Al5 Al6 Al7 Bh0 Bh1 Bh2 Bh3 Bh4 Bh5 Bh6 \
        Bh7 Bl0 Bl1 Bl2 Bl3 Bl4 Bl5 Bl6 Bl7 CinH CinL CoutH CoutL SumH0 \
        SumH1 SumH2 SumH3 SumH4 SumH5 SumH6 SumH7 SumL0 SumL1 SumL2 SumL3 \
        SumL4 SumL5 SumL6 SumL7 Vdd Vdd\- Vss Vss\+
    I11 (Ah3 Al3 Bh3 Bl3 net117 net118 net131 net132 SumH3 SumL3 Vdd Vdd\- \
        Vss Vss\+) SupplyBiasFullAdder
    I12 (Ah4 Al4 Bh4 Bl4 net103 net104 net117 net118 SumH4 SumL4 Vdd Vdd\- \
        Vss Vss\+) SupplyBiasFullAdder
    I13 (Ah5 Al5 Bh5 Bl5 net89 net90 net103 net104 SumH5 SumL5 Vdd Vdd\- \
        Vss Vss\+) SupplyBiasFullAdder
    I14 (Ah6 Al6 Bh6 Bl6 net75 net76 net89 net90 SumH6 SumL6 Vdd Vdd\- Vss \
        Vss\+) SupplyBiasFullAdder
    I15 (Ah7 Al7 Bh7 Bl7 CoutH CoutL net75 net76 SumH7 SumL7 Vdd Vdd\- Vss \
        Vss\+) SupplyBiasFullAdder
    I8 (Ah0 Al0 Bh0 Bl0 net159 net160 CinH CinL SumH0 SumL0 Vdd Vdd\- Vss \
        Vss\+) SupplyBiasFullAdder
    I9 (Ah1 Al1 Bh1 Bl1 net145 net146 net159 net160 SumH1 SumL1 Vdd Vdd\- \
        Vss Vss\+) SupplyBiasFullAdder
    I10 (Ah2 Al2 Bh2 Bl2 net131 net132 net145 net146 SumH2 SumL2 Vdd Vdd\- \
        Vss Vss\+) SupplyBiasFullAdder
ends Project_8BitRippleCarryAdder_schematic
// End of subcircuit definition.

// Library name: Project
// Cell name: AdderBuffer
// View name: schematic
subckt AdderBuffer Ah Al OutH OutL Vdd Vdd\- Vss Vss\+
    M1 (OutL Ah Vss Vss) NMOS_VTL w=360.0n l=50n as=3.78e-14 ad=3.78e-14 \
        ps=570.0n pd=570.0n ld=105n ls=105n m=1
    M0 (OutH Ah Vss\+ Vss\+) NMOS_VTL w=360.0n l=50n as=3.78e-14 \
        ad=3.78e-14 ps=570.0n pd=570.0n ld=105n ls=105n m=1
    M3 (OutL Al Vdd\- Vdd\-) PMOS_VTL w=720.0n l=50n as=7.56e-14 \
        ad=7.56e-14 ps=930.0n pd=930.0n ld=105n ls=105n m=1
    M2 (OutH Al Vdd Vdd) PMOS_VTL w=720.0n l=50n as=7.56e-14 ad=7.56e-14 \
        ps=930.0n pd=930.0n ld=105n ls=105n m=1
ends AdderBuffer
// End of subcircuit definition.

// Library name: Project
// Cell name: 8BitAdder_TB
// View name: schematic
I0 (net23 net25 net27 net29 net31 net33 net35 net37 net24 net26 net28 \
        net30 net32 net34 net36 net38 net39 net41 net43 net45 net47 net49 \
        net51 net53 net40 net42 net44 net46 net48 net50 net52 net54 net55 \
        net56 coutH coutL sumH0 sumH1 sumH2 sumH3 sumH4 sumH5 sumH6 sumH7 \
        sumL0 sumL1 sumL2 sumL3 sumL4 sumL5 sumL6 sumL7 net095 net5 \
        net0400 net0221) Project_8BitRippleCarryAdder_schematic
I34 (net0104 net0105 CoutH CoutL net095 net5 net0400 net0221) AdderBuffer
I33 (coutH coutL net0104 net0105 net095 net5 net0400 net0221) AdderBuffer
I32 (net0120 net0121 SumH0 SumL0 net095 net5 net0400 net0221) AdderBuffer
I31 (sumH0 sumL0 net0120 net0121 net095 net5 net0400 net0221) AdderBuffer
I30 (net0136 net0137 SumH7 SumL7 net095 net5 net0400 net0221) AdderBuffer
I29 (sumH7 sumL7 net0136 net0137 net095 net5 net0400 net0221) AdderBuffer
I28 (net0152 net0153 SumH6 SumL6 net095 net5 net0400 net0221) AdderBuffer
I27 (sumH6 sumL6 net0152 net0153 net095 net5 net0400 net0221) AdderBuffer
I26 (net0168 net0169 SumH5 SumL5 net095 net5 net0400 net0221) AdderBuffer
I25 (sumH5 sumL5 net0168 net0169 net095 net5 net0400 net0221) AdderBuffer
I24 (net0184 net0185 SumH1 SumL1 net095 net5 net0400 net0221) AdderBuffer
I23 (sumH1 sumL1 net0184 net0185 net095 net5 net0400 net0221) AdderBuffer
I22 (net0200 net0201 SumH4 SumL4 net095 net5 net0400 net0221) AdderBuffer
I21 (sumH4 sumL4 net0200 net0201 net095 net5 net0400 net0221) AdderBuffer
I20 (net0216 net0217 SumH3 SumL3 net095 net5 net0400 net0221) AdderBuffer
I19 (sumH3 sumL3 net0216 net0217 net095 net5 net0400 net0221) AdderBuffer
I18 (net0232 net0233 SumH2 SumL2 net095 net5 net0400 net0221) AdderBuffer
I17 (sumH2 sumL2 net0232 net0233 net095 net5 net0400 net0221) AdderBuffer
I68 (net55 net56 net0248 net0249 net0271 net0324 net0262 net0881) DelVGate
I67 (net0248 net0249 Cin Cin net0271 net0324 net0262 net0881) DelVGate
I66 (net53 net54 net0264 net0265 net0271 net0324 net0262 net0881) DelVGate
I65 (net0264 net0265 B7 B7 net0271 net0324 net0262 net0881) DelVGate
I64 (net51 net52 net0280 net0281 net0271 net0324 net0262 net0881) DelVGate
I63 (net0280 net0281 B6 B6 net0271 net0324 net0262 net0881) DelVGate
I62 (net49 net50 net0296 net0297 net0271 net0324 net0262 net0881) DelVGate
I61 (net0296 net0297 B5 B5 net0271 net0324 net0262 net0881) DelVGate
I60 (net47 net48 net0312 net0313 net0271 net0324 net0262 net0881) DelVGate
I59 (net0312 net0313 B4 B4 net0271 net0324 net0262 net0881) DelVGate
I58 (net45 net46 net0328 net0329 net0271 net0324 net0262 net0881) DelVGate
I57 (net0328 net0329 B3 B3 net0271 net0324 net0262 net0881) DelVGate
I56 (net43 net44 net0344 net0345 net0271 net0324 net0262 net0881) DelVGate
I55 (net0344 net0345 B2 B2 net0271 net0324 net0262 net0881) DelVGate
I54 (net41 net42 net0360 net0361 net0271 net0324 net0262 net0881) DelVGate
I53 (net0360 net0361 B1 B1 net0271 net0324 net0262 net0881) DelVGate
I52 (net39 net40 net0376 net0377 net0271 net0324 net0262 net0881) DelVGate
I51 (net0376 net0377 B0 B0 net0271 net0324 net0262 net0881) DelVGate
I50 (net37 net38 net0392 net0393 net0271 net0324 net0262 net0881) DelVGate
I49 (net0392 net0393 A7 A7 net0271 net0324 net0262 net0881) DelVGate
I48 (net35 net36 net0408 net0409 net0271 net0324 net0262 net0881) DelVGate
I47 (net0408 net0409 A6 A6 net0271 net0324 net0262 net0881) DelVGate
I46 (net33 net34 net0424 net0425 net0271 net0324 net0262 net0881) DelVGate
I45 (net0424 net0425 A5 A5 net0271 net0324 net0262 net0881) DelVGate
I44 (net31 net32 net0440 net0441 net0271 net0324 net0262 net0881) DelVGate
I43 (net0440 net0441 A4 A4 net0271 net0324 net0262 net0881) DelVGate
I42 (net29 net30 net0456 net0457 net0271 net0324 net0262 net0881) DelVGate
I41 (net0456 net0457 A3 A3 net0271 net0324 net0262 net0881) DelVGate
I40 (net27 net28 net0472 net0473 net0271 net0324 net0262 net0881) DelVGate
I39 (net0472 net0473 A2 A2 net0271 net0324 net0262 net0881) DelVGate
I38 (net25 net26 net0488 net0489 net0271 net0324 net0262 net0881) DelVGate
I37 (net0488 net0489 A1 A1 net0271 net0324 net0262 net0881) DelVGate
I36 (net23 net24 net0504 net0505 net0271 net0324 net0262 net0881) DelVGate
I35 (net0504 net0505 A0 A0 net0271 net0324 net0262 net0881) DelVGate
V7 (net0400 0) vsource dc=-delv type=dc
V6 (net0881 0) vsource dc=- delv type=dc
V5 (net0221 0) vsource dc=delv type=dc
V4 (net5 0) vsource dc=vdd - delv type=dc
V3 (net095 0) vsource dc=vdd + delv type=dc
V2 (net0262 0) vsource dc=delv type=dc
V1 (net0324 0) vsource dc=vdd - delv type=dc
V0 (net0271 0) vsource dc=vdd + delv type=dc
